F5 LTM - RAM Cache


RAM Cache is a feature that provides the ability to serve content to your clients directly from the memory of your F5 appliance.
This benefits both client and server by reducing response latency and also server load.

What is Cached ?

Heres a summary,

The following items are cached,

  • All 200, 203, 206, 300, 301, and 410 responses to a GET request method by default.
  • Other HTTP methods can be cached via the URI URI Include list or an iRule.

The following items are not cached,

  • Private data defined by cache control headers
  • HTTP methods HEAD, PUT, DELETE, TRACE, and CONNECT are not cached by default.

For a full list of the items that can and cannot be cached please see here.


RAM Cache is configured within the HTTP profile (Local Traffic / Profiles / Services / HTTP). This is then assigned to your Virtual Server via the dropdown "HTTP Profile".

  • RAM Cache  - Disables / enables the feature
  • Maximum Cache Size - The maximum size (in Megabytes) for RAM cache. When the maximum size is reached the oldest entries are removed first.
  • Maximum Entries - The maximum number of entries that can be in RAM Cache.
  • Maximum Age - The maximum period that the entry will be cached for. However this value is ignored if the "Cache Control Headers" specify that the entry has expired.
  • Minimum Object Size - Minimum size of item that can be cached.
  • Maximum Object Size - Maximum size of item that can be cached.
  • URI Caching - provides further granularity into what should/shouldn't be cached. The order of preference is Exclude List, Pin List, Include List.
  • Pin List: Defines what items should be cached indefinitely (ignoring the expiry headers) that are not cached by default.
  • Include List: Defines what items should be cached that are not cached by default.
  • Exclude List: Based on the items that are cached by default, this list defines what items should not be excluded (i.e not cached)
  • Ignore Headers - Defines how "Cache-Control" headers should be ignored.
  • Insert Age Header - Defines whether a date and age headers should be added. The date provides the date on the F5 and the age provides the time the item has been in cache.
  • Aging Rate - Defines how quickly the system ages a cached item. 0 (slowest) / 10 (fastest)

Memory Considerations

By default the maximum cache size is 100MB. However due to CMP (Clustered Multi-Processing) this is per TMM instance. Meaning on a system with 2 cores this would relate to 200MB.

Note : CMP basically runs a separate TMM instance on each CPU core which provides benefits in performance.

Taking this in to consideration, the system allows for a maximum of 50% of free RAM to be assigned to RAM Cache.

[root@f5ltm:Active] config # b db show | grep MaxMemoryPercent
Ramcache.MaxMemoryPercent = 50


Taking the above into account, to calculate the largest maximum cache size you would first check the amount of free RAM on the device by using the following command,

root@f5ltm(Active)(tmos)# show sys memory

Sys::System Memory Information
Memory Used(bytes)  Current  Average  Max(since 06/08 10:13)
Total Phys Memory      3.8G     3.8G                    3.8G
OS Used Memory         3.8G     3.8G                    3.8G
TMM Alloc Memory       2.9G     2.9G                    2.9G
TMM Used Memory        800M     801M                    801M

Here we can see that we have 2.1G free. Only 50% of this can be assigned to RAM Cache which is 1050MB. As we are basing our example on a 1600 LTM which has 2 cores, the maximum cache size would be 525Mb.


Note : you will need to replace the name of your profile from PROF-RAMCACHE to whatever your profile is named.

show commands

Here are the main show commands. The 'show ltm profile ramcache ....' commands show the relating entries. Whereas the 'show ltm profile http ....' command shows the statistics for the profile.

root@f5ltm(Active)(tmos)# show ltm profile ramcache PROF-RAMCACHE
root@f5ltm(Active)(tmos)# show ltm profile ramcache PROF-RAMCACHE uri <VALUE>
root@f5ltm(Active)(tmos)# show ltm profile ramcache PROF-RAMCACHE host <VALUE>
root@f5ltm(Active)(tmos)# show ltm profile http PROF-RAMCACHE

delete commands

Below provides you with the commands required should you which to remove cached entries. The top command would be used to clear all entries for a given profile.

root@f5ltm(Active)(tmos)# delete ltm profile ramcache PROF-RAMCACHE
root@f5ltm(Active)(tmos)# delete ltm profile ramcache PROF-RAMCACHE uri <VALUE>
root@f5ltm(Active)(tmos)# delete ltm profile ramcache PROF-RAMCACHE host <VALUE> uri <VALUE>

NOTE   When viewing the RAMCache via TMSH entries using show ltm profile PROF-RAMCACHE will not include the details of any query strings within the URI field. To show the details of the query string within the URI use the command show ltm profile PROF-RAMCACHE all uri sales/bananas

iRule Commands

There are a number of iRule commands and events that can be used to control the RAM cache feature. These can be found at,

However, out of all of the iRule CACHE commands the most useful is 'CACHE::userkey <key>'. This provides the ability to add a key value to cached entries on the F5. This allows for multiple instances of an object to be cached. In turn providing greater granularity then what the HTTP header 'vary' can offer, i.e storing different cache entries based on HTTP headers.

Below is an example. Here if the HTTP path starts with /cacti then a cached instance of the object is served and also stored using a key value based on either BLUE or YELLOW (i.e dependent on the value  to the header 'TEST').

    if { [HTTP::path] starts_with "/cacti" } {
        if { [HTTP::header value TEST] eq "yellow" } {
            CACHE::userkey YELLOW }
        elseif { [HTTP::header value TEST] eq "blue" } {
            CACHE::userkey BLUE

To confirm the number of cached entry variations within the cache the following command can be used 'show ltm profile ramcache PROF-RAMCACHE host <VALUE>'.

URI : /cacti/images/auth_login.gif
  Source Slot/TMM  0/0
  Owner Slot/TMM   0/0
  Rank             1

  Size (bytes)     21532
  Hits             0
  Received         2013-12-17 21:56:17
  Last Sent        2013-12-17 21:56:17
  Expires          2013-12-17 22:56:18
  Vary Type        none
  Vary Count       2
  Vary User Agent  none
  Vary Encoding    none
Total records returned: 1



Tags: BIG-IP F5, RAMCache

About the Author


R Donato

Rick Donato is the Founder and Chief Editor of He currently works as a Principal Network Security Engineer and has a keen interest in automation and the cloud.

You can find Rick on Twitter @f3lix001